In current metal oxide semiconductor field effect transistors (MOSFETs), a polysilicon gate is typically employed. One disadvantage of utilizing polysilicon gates is that at inversion, the polysilicon gates generally experience depletion of carriers in the area of the polysilicon gate that is adjacent to the gate dielectric. This depletion of carriers is referred to in the art as the polysilicon depletion effect. The depletion effect reduces the effective gate capacitance of the MOSFET. Ideally, it is desirable that the gate capacitance of the MOSFET be high since high gate capacitance typically equates to more charge being accumulated. As more charge is accumulated in the channel, the source/drain current becomes higher when the transistor is biased.
MOSFETs including a gate stack comprising a bottom polysilicon portion and a top silicide portion are also known. The layer of silicide in such a gate stack contributes to a decrease in the resistance of the gate. The decrease in resistance causes a decrease in the time propagation delay RC of the gate. Although a silicide top gate region may help decrease the resistance of the transistor, charge is still depleted in the vicinity of the interface formed between the bottom polysilicon gate and gate dielectric, thereby causing a smaller effective gate capacitance.
Another type of MOSFET that is available is one where the gate electrode is made entirely of a metal. In such MOSFETs, the metal of the gate prevents depletion of charge through the gate. This prevents the increase in effective thickness of the gate capacitor and the capacitance decreases as a result of the depletion effect.
Although metal gates can be used to eliminate the poly-depletion effect and to provide lower gate resistance, it is generally quite difficult to offer multiple-threshold voltages with metal gates. Multiple-threshold voltages are needed in the semiconductor industry in order to provide design flexibility for low-power, high-performance, and mixed-signal applications for overall system performance.
U.S. Pat. No. 6,204,103 to Bai, et al. disclose a method for forming first and second transistor devices. This prior art method includes the steps of forming a first region of silicide over a portion of a gate dielectric that overlies a first well region in a semiconductor substrate; forming a second region of silicide over a second portion of the gate dielectric that overlies a second well region in the substrate; and forming first and second doped regions in the first and second well regions.
In Bai, et al., different metals are employed in forming the first and second silicide regions. The prior art does not disclose the use of a bimetal layer in forming one of the silicide regions, nor does it disclose a process where metal alloys are used. Bai, et al. does make a general statement, See Col. 5, lines 22-24, that “metals may exist at a desired Fermi level in their natural state or by chemical reactions such as alloying, doping, etc.” No disclosure of using metal alloys in this prior art process is however made.
In current CMOS technology, impurity doping into the body of the MOSFET via ion implantation is employed for short-channel effect control and threshold voltage tuning. However, carrier mobility is degraded with ever increasing impurity doping which, in turn, degrades the device performance. The threshold voltage variations due to doping fluctuation will also limit the effectiveness of the doping technique. It is therefore highly desirable to provide an alternative way to adjust the threshold voltage in metal gated MOSFETs.